View PCA9564D_4478114.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

philips semiconductors pca9564 parallel bus to i 2 c-bus controller product data supersedes data of 2003 feb 26 2003 apr 02 integrated circuits
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2 2003 apr 02 features ? parallel-bus to i 2 c-bus protocol converter and interface ? both master and slave functions ? multi-master capability ? internal oscillator reduces external components ? operating supply voltage 2.3 v to 3.6 v ? 5 v tolerant i/os ? standard and fast mode i 2 c capable and compatible with smbus ? esd protection exceeds 2000 v hem per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceed 100 ma. ? packages offered: so20, tssop20, hvqfn20 applications ? add i 2 c bus port to controllers/processors that don?t have one ? add additional i 2 c bus ports to controllers/processors that need multiple i 2 c bus ports ? higher frequency, lower voltage migration path for the pcf8584 ? converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire pc board description the pca9564 is an integrated circuit designed in cmos technology that serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial i 2 c-bus and allows the parallel bus system to communicate bi-directionally with the i 2 c-bus. the pca9564 can operate as a master or a slave and can be a transmitter or receiver. communication with the i 2 c-bus is carried out on a byte-wise basis using interrupt or polled handshake. the pca9564 controls all the i 2 c-bus specific sequences, protocol, arbitration and timing with no external timing element required. the pca9564 is similar to the pcf8584 but operates at lower voltages and higher i c frequencies. other enhancements requested by design engineers have also been incorporated. characteristic pca9564 pcf8584 comments voltage range 2.3-3.6 v 4.5-5.5 v pca9564 is 5 v tolerant maximum master mode i 2 c frequency 360 khz 90 khz faster i 2 c interface maximum slave mode i 2 c frequency 400 khz 100 khz faster i 2 c interface clock source internal external less expensive and more flexible with internal oscillator parallel interface fast 50 mhz slow compatible with faster processors while the pcf8584 supported most parallel-bus microcontrollers/ microprocessors including the intel 8049/8051, motorola 6800/68000 and the zilog z80, the pca9564 has been designed to be very similar to the philips standard 80c51 microcontroller i 2 c hardware so the devices are not code compatible. additionally, the pca9564 does not support the bus monitor ?snoop? mode nor the long distance mode and is not foot print compatible with the pcf8584. ordering information packages temperature range order code topside mark drawing number 20-pin plastic so -40 to +85 c PCA9564D PCA9564D sot163-1 20-pin plastic tssop -40 to +85 c pca9564pw pca9564 sot360-1 20-pin plastic hvqfn -40 to +85 c pca9564bs 9564 sot662-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 3 pin configuration ? so, tssop 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 d0 d1 d2 d3 d4 d5 d6 d7 dnu v ss v dd sda scl reset int a1 a0 rd ce wr 10 su01485 pin configuration ? hvqfn 15 14 13 12 11 6 7 8 9 10 1 2 3 4 5 20 19 18 17 16 su01665 top view d2 d3 d4 d5 d6 d7 dnu gnd (v ss ) wr rd ce int reset a0 a1 scl sda v dd d0 d1 pin configuration pin number so, tssop hvqfn symbol pin type name and function 1, 2, 3, 4, 5, 6, 7, 8 1, 2, 3, 4, 5, 18, 19, 20 d0-d7 i/o data bus: bi-directional 3-state data bus used to transfer commands, data and status between the controller and the cpu. d0 is the least significant bit. 9 6 dnu do not use: must be left floating (pulled low internally) 10 7 v ss pwr ground 11 8 wr i write strobe: when low and ce is also low, the contents of the data bus is loaded into the addressed register. the transfer occurs on the rising edge of the signal. 12 9 rd i read strobe: when low and ce is also low, causes the contents of the addressed register to be presented on the data bus. the read cycle begins on the falling edge of rd . 13 10 ce i chip enable: active-low input signal. when low, data transfers between the cpu and the controller are enabled on d0-d7 as controlled by the wr , rd and a0-a1 inputs. when high, places the d0-d7 lines in the 3-state condition. 14, 15 11, 12 a0, a1 i address inputs: selects the controller internal registers and ports for read/write operations. 16 13 int o interrupt request: active-low, open-drain, output. this pin requires a pull-up device. 17 14 reset i reset: a low level clears internal registers resets the i 2 c state machine. 18 15 scl i/o i 2 c-bus serial clock input/output (open-drain). 19 16 sda i/o i 2 c-bus serial data input/output (open-drain). 20 17 v dd pwr power supply: 2.3 to 3.6 v
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 4 8 d0-d7 rd wr ce a0 reset int bus buffer operation control address decode r/w control interrupt control timing clock selectors scl sda v dd v ss control timing internal databus sd00707 internal oscillator a1 pca9564 master/slave state machines input filter power-on reset figure 1. block diagram
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 5 functional description general the pca9564 acts as an interface device between standard high-speed parallel buses and the serial i 2 c-bus. on the i 2 c-bus, it can act either as master or slave. bidirectional data transfer between the i 2 c-bus and the parallel-bus microcontroller is carried out on a byte-wise basis, using either an interrupt or polled handshake. internal oscillator the pca9564 contains an internal 9 mhz oscillator which is used for all i 2 c timing. the oscillator requires up to 500 s to start-up after ensio bit is set to ? 1 ? . registers the pca9564 contains four registers which are used to configure the operation of the device as well as to send and receive serial data. the registers are selected by setting pins a0 and a1 to the appropriate logic levels before a read or write operation is executed. caution: do not write to i 2 c registers while the i 2 c-bus is busy and the sio is in master or addressed slave mode. register name register function a1 a0 read/ write default i2csta status 0 0 r f8h i2cto time-out 0 0 w ffh i2cdat data 0 1 r/w 00h i2cadr own address 1 0 r/w 00h i2ccon control 1 1 r/w 00h the time-out register, i2cto: the time-out register is used to determine the maximum time that scl is allowed to be low before the i 2 c state machine is reset. when the i 2 c interface is operating, i2cto is loaded in the time-out counter at every scl transition. i2cto te time-out value 76 5 4 3 2 1 0 to6 to5 to4 to3 to2 to1 to0 the most significant bit of i2cto (te) is used as a time-out enable/disable. a ? 1 ? will enable the time-out function. the time-out period = (i2cto[6:0] + 1) 113.7 s. the time-out value may vary some and is an approximate value. the time-out register can be used in the following cases: 1. when the sio, in the master mode, wants to send a start condition and the scl line is held low by some other device. the sio waits a time period equivalent to the time-out value for the scl to be released. in case it is not released, the sio concludes that there is a bus error, loads 90h in the i2csta register, generates an interrupt signal and releases the scl and sda lines. after the microcontroller reads the status register, it needs to send an external reset in order to reset the sio. 2. in the master mode, the time-out feature starts every time the scl goes low. if scl stays low for a time period equal to or greater than the time-out value, the sio concludes there is a bus error and behaves in the manner described above. 3. in case of a forced access to the i 2 c-bus. (see more details on page 15.) the address register, i2cadr: i2cadr is not affected by the sio hardware. the contents of this register are irrelevant when sio is in a master mode. in the slave modes, the seven most significant bits must be loaded with the microcontroller ? s own slave address. i2cadr 0 7 65 432 10 own slave address bit7 bit6 bit5 bit4 bit3 bit2 bit1 the most significant bit corresponds to the first bit received from the i 2 c-bus after a start condition. a logic 1 in i2cadr corresponds to a high level on the i 2 c-bus, and a logic 0 corresponds to a low level on the bus. the least significant bit is not used but should be programmed with a ? 0 ? . the data register, i2cdat: i2cdat contains a byte of serial data to be transmitted or a byte which has just been received. in master mode, this includes the slave address that the master wants to send out on the i 2 c-bus, with the most significant bit of the slave address in the sd7 bit position and the read/write bit in the sd0 bit position. the cpu can read from and write to this 8-bit register while it is not in the process of shifting a byte. this occurs when sio is in a defined state and the serial interrupt flag is set. data in i2cdat remains stable as long as si is set. whenever the sio generates an interrupt, the i2cdat registers contain the data byte that was just transferred on the i 2 c-bus. note: the i2cdat register will capture the serial address as data when addressed via the serial bus. also, the data register will continue to capture data from the serial bus during 38h so the i2cdat register will need to be reloaded when the bus becomes free. i2cdat sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 7 65 43 2 1 0 ? sd7 - sd0: eight bits to be transmitted or just received. a logic 1 in i2cdat corresponds to a high level on the i 2 c-bus, and a logic 0 corresponds to a low level on the bus. the control register, i2ccon: the microcontroller can read from and write to this 8-bit register. two bits are affected by the sio hardware: the si bit is set when a serial interrupt is requested, and the sto bit is cleared when a stop condition is present on the i 2 c-bus. i2ccon ensio sta sto si cr1 cr0 7 6543210 cr2 aa ? ensio , the sio e nable b it ensio = ? 0 ? : when ensio is ? 0 ? , the sda and scl outputs are in a high impedance state. sda and scl input signals are ignored, sio is in the ? not addressed ? slave state. ensio = ? 1 ? : when ensio is ? 1 ? , sio is enabled. after the ensio bit is set, it takes 500 s for the internal oscillator to start up, therefore, the pca9564 will enter either the master or the slave mode after this time. ensio should not be used to temporarily release the pca9564 from the i 2 c-bus since, when ensio is reset, the i 2 c-bus status is lost. the aa flag should be used instead (see description of the aa flag in the following text). in the following text, it is assumed that ensio = ? 1 ? . ? sta , the start f lag
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 6 sta = ? 1 ? : when the sta bit is set to enter a master mode, the sio hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free. if the bus is not free, then sio waits for a stop condition (which will free the bus) and generates a start condition after the minimum buffer time (t buf ) has elapsed. if sta is set while sio is already in a master mode and one or more bytes are transmitted or received, sio transmits a repeated start condition. sta may be set at any time. sta may also be set when sio is an addressed slave. sta = ? 0 ? : when the sta bit is reset, no start condition or repeated start condition will be generated. ? sto , the stop f lag sto = ? 1 ? : when the sto bit is set while sio is in a master mode, a stop condition is transmitted to the i 2 c-bus. when the stop condition is detected on the bus, the sio hardware clears the sto flag. if the sta and sto bits are both set, then a stop condition is transmitted to the i 2 c-bus if sio is in a master mode. sio then transmits a start condition. sto = ? 0 ? : when the sto bit is reset, no stop condition will be generated. ? si , the s erial i nterrupt f lag si = ? 1 ? : when the si flag is set, then, if the ensio bit is also set, a serial interrupt is requested. si is set by hardware when one of 24 of the 25 possible sio states is entered. the only state that does not cause si to be set is state f8h, which indicates that no relevant state information is available. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. a high level on the scl line is unaffected by the serial interrupt flag. si must be reset by writing ? 0 ? to the si bit. the si bit cannot be set by the user. si = ? 0 ? : when the si flag is reset, no serial interrupt is requested, and there is no stretching of the serial clock on the scl line. ? aa , the a ssert a cknowledge f lag aa = ? 1 ? : if the aa flag is set, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line when: - the ? own slave address ? has been received - a data byte has been received while sio is in the master receiver mode - a data byte has been received while sio is in the addressed slave receiver mode aa = ? 0 ? : if the aa flag is reset, a not acknowledge (high level to sda) will be returned during the acknowledge clock pulse on scl when: - a data byte has been received while sio is in the master receiver mode - a data byte has been received while sio is in the addressed slave receiver mode - ? own slave address ? has been received when sio is in the addressed slave transmitter mode, state c8h will be entered after the last serial is transmitted (see figure 5). when si is cleared, enters the not addressed slave receiver mode, and the sda line remains at a high level. in state c8h, the aa flag can be set again for future address recognition. when sio is in the not addressed slave mode, its own slave address is ignored. consequently, no acknowledge is returned, and a serial interrupt is not requested. thus, sio can be temporarily released from the i 2 c-bus while the bus status is monitored. while sio is released from the bus, start and stop conditions are detected, and serial data is shifted in. address recognition can be resumed at any time by setting the aa flag. ? t he c lock r ate b its, cr 2, cr 1, and cr 0 three bits determine the serial clock frequency when sio is in master mode. the various serial rates are shown in table 1. the clock frequencies only take the high and low times into consideration. the rise and fall time will cause the actual measured frequency to be lower than expected. the frequencies shown in table 1 are unimportant when sio is in a slave mode. in the slave modes, sio will automatically synchronize with any clock frequency up to 400 khz. table 1. serial clock rates cr2 cr1 cr0 serial clock frequency (khz) 0 0 0 330 0 0 1 288 0 1 0 217 0 1 1 146 1 0 0 88 1 1 0 1 59 1 1 0 44 1 1 1 36 note: 1. the clock frequency values are approximate and may vary with temperature, supply voltage, process, and scl output loading. if normal mode i 2 c parameters must be strictly followed (scl < 100khz), it is recommended not to use cr[2:0] = 100 (scl = 88khz) since the clock frequency might be slightly higher than 100 khz under certain temperature, voltage, and process conditions and use cr[2:0] = 101 (scl = 59 khz) instead. the status register, i2csta: i2csta is an 8-bit read-only register. the three least significant bits are always zero. the five most significant bits contain the status code. there are 25 possible status codes. when i2csta contains f8h, no relevant state information is available and no serial interrupt is requested. all other i2csta values correspond to defined sio states. when each of these states is entered, a serial interrupt is requested (si = ? 1 ? ). more information on sio operating modes the four operating modes are: - master transmitter - master receiver - slave receiver - slave transmitter data transfers in each mode of operation are shown in figures 2-5. these figures contain the following abbreviations:
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 7 abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition in figures 2-5, circles are used to indicate when the serial interrupt flag is set. a serial interrupt is not generated when i2csta = f8h. this happens on a stop condition. the numbers in the circles show the status code held in the i2csta register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in i2csta is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables 2-6. master transmitter mode: in the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see figure 2). before the master transmitter mode can be entered, i2ccon must be initialized as follows: i2ccon ensio sta sto si cr1 cr0 7 6543210 1000 x bit rate cr2 aa ensio must be set to logic 1 to enable sio. if the aa bit is reset, sio will not acknowledge its own slave address in the event of another device becoming master of the bus. in other words, if aa is reset, sio cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit. the sio logic will now test the i 2 c-bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the serial interrupt flag (si) is set, and the status code in the status register (i2csta) will be 08h. this status code must be used to vector to an interrupt service routine that loads i2cdat with the slave address and the data direction bit (sla+w). the si bit in i2ccon must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in i2csta are possible. there are 18h, 20h, or 38h for the master mode and also 68h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 2. after a repeated start condition (state 10h). sio may switch to the master receiver mode by loading i2cdat with sla+r). note that a master should never transmit its own slave address. master receiver mode: in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 3). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load i2cdat with the 7-bit slave address and the data direction bit (sla+r). the si bit in i2ccon must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in i2csta are possible. these are 40h, 48h, or 38h for the master mode and also 68h, or b0h if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for each of these status codes is detailed in table 3. ensio is not affected by the serial transfer and are not referred to in table 3. after a repeated start condition (state 10h), sio may switch to the master transmitter mode by loading i2cdat with sla+w. note that a master should not transmit its own slave address. slave receiver mode: in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 4). to initiate the slave receiver mode, i2cadr and i2ccon must be loaded as follows: i2cadr 0 7 65 432 1 0 own slave address bit7 bit6 bit5 bit4 bit3 bit2 bit1 the upper 7 bits are the address to which sio will respond when addressed by a master. i2ccon ensio sta sto si 7 6543210 11 000xx x aa cr1 cr0 cr2 ensio must be set to logic 1 to enable sio. the aa bit must be set to enable sio to acknowledge its own slave address, sta, sto, and si must be reset. when i2cadr and i2ccon have been initialized, sio waits until it is addressed by its own slave address followed by the data direction bit which must be ? 0 ? (w) for sio to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (i) is set and a valid status code can be read from i2csta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 4. the slave receiver mode may also be entered if arbitration is lost while sio is in the master mode (see status 68h). if the aa bit is reset during a transfer, sio will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, sio does not respond to its own slave address. however, the i 2 c-bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio from the i 2 c-bus.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 8 ???????? ???????? ??? ??? ??? ??? ??? ??? s sla wa a data p ??????? ??????? ??????? s sla w ??? ??? a p ??? ??? ??? a p 08h 18h 28h ??? ??? r 38h a or a other mst continues a or a other mst continues 38h 30h 20h b0h other mst continues a mt 10h to mst/rec mode entry = mr successful transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave ???? ???? ???? ???? ??? ??? ??? ?? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in i2csta) corresponds to a defined state of the i 2 c bus. see table 2. data sw00816 68h to corresponding states in slave receiver mode to corresponding states in slave transmitter mode note: the master should never transmit its own slave address f8h f8h f8 figure 2. format and states in the master transmitter mode
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 9 ???????? ???????? ??? ??? s sla ra data p ??????? ??????? ??????? s sla r ??? ??? a p 08h 40h 50h ??? ??? w 38h a or a other mst continues other mst continues 38h 48h other mst continues a mr 10h to mst/trx mode entry = mt successful reception from a slave transmitter next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or acknowledge bit arbitration lost and addressed as slave ???? ???? ???? ???? ???? n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in i2csta) corresponds to a defined state of the i 2 c bus. see table 3. ??? ??? a ???? ???? data ??? ??? a 58h ??? ??? a ?? ?? data a sw00817 b0h 68h to corresponding states in slave receiver mode to corresponding states in slave transmitter mode f8h f8h figure 3. format and states in the master receiver mode
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 10 ??????? ??????? ??????? ??? ??? ??? ???? ???? ???? ??? ??? ??? s sla wa a data p or s a 60h 80h 68h reception of the own slave address and one or more data bytes all are acknowledged. last data byte received is not acknowledged arbitration lost as mst and addressed as slave ???? ???? ???? ???? ??? ??? ?? ?? a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in i2csta) corresponds to a defined state of the i 2 c bus. see table 4. data a sla ??? ??? ??? data 80h a0h ??? ??? ??? a 88h p or s sw00814 ??? ??? ??? p or s on stop f8h on stop f8h figure 4. format and states in the slave receiver mode ???????? ???????? ???????? ??? ??? ??? ??? ??? ??? ???? ???? ???? ??? ??? ??? s sla ra data p or s b0h a8h b8h reception of the own slave address and transmission of one or more data bytes a data a c0h ???? ???? ???? ?? ?? ?? n any number of data bytes and their associated acknowledge bits this number (contained in i2csta) corresponds to a defined state of the i 2 c bus. see table 5. data a ??? ??? ??? all ? 1 ? s ??? ??? ??? a a ???? ???? ???? from master to slave from slave to master c8h p or s last data byte transmitted. switched to not addressed slave (aa bit in i2ccon = ? 0 ? ) arbitration lost as mst and addressed as slave sw00815 f8h on stop f8h on stop figure 5. format and states of the slave transmitter mode
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 11 table 2. master transmitter mode application software response status code status of the i 2 c bus and to i2ccon next action taken by sio hardware (i2csta) sio hardware to/from i2cdat sta sto si aa 08h a start condition has been transmitted load sla+w x x 0 x sla+w will be transmitted; ack bit will be received 10h a repeated start load sla+w or x x 0 x as above condition has been transmitted load sla+r x x 0 x sla+r will be transmitted; sio will be switched to mst/rec mode 18h sla+w has been transmitted; ack has load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received been received no i2cdat action or 1 0 0 x repeated start will be transmitted; no i2cdat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no i2cdat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 20h sla+w has been transmitted; not ack load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received has been received no i2cdat action or 1 0 0 x repeated start will be transmitted; no i2cdat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no i2cdat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 28h data byte in i2cdat has been transmitted; load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received ack has been received no i2cdat action or 1 0 0 x repeated start will be transmitted; no i2cdat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no i2cdat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 30h data byte in i2cdat has been transmitted; load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received not ack has been no i2cdat action or 1 0 0 x repeated start will be transmitted; received no i2cdat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no i2cdat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+w or no i2cdat action or 0 0 0 x i 2 c-bus will be released; not addressed slave will be entered data bytes no i2cdat action 1 0 0 x a start condition will be transmitted when the bus becomes free (stop or scl and sda high)
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 12 table 3. master receiver mode application software response status code status of the i 2 c bus and to i2ccon next action taken by sio hardware (i2csta) sio hardware to/from i2cdat sta sto si aa 08h a start condition has been transmitted load sla+r x x 0 x sla+r will be transmitted; ack bit will be received 10h a repeated start load sla+r or x x 0 x as above condition has been transmitted load sla+w x x 0 x sla+w will be transmitted; sio will be switched to mst/trx mode 38h arbitration lost in not ack bit no i2cdat action or 0 0 0 x i 2 c-bus will be released; sio will enter a slave mode no i2cdat action 1 0 0 x a start condition will be transmitted when the bus becomes free 40h sla+r has been transmitted; ack has no i2cdat action or 0 0 0 0 data byte will be received; not ack bit will be returned been received no i2cdat action 0 0 0 1 data byte will be received; ack bit will be returned 48h sla+r has been no i2cdat action or 1 0 0 x repeated start condition will be transmitted transmitted; not ack has been received no i2cdat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset no i2cdat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 50h data byte has been received; ack has been read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned returned read data byte 0 0 0 1 data byte will be received; ack bit will be returned 58h data byte has been read data byte or 1 0 0 x repeated start condition will be transmitted received; not ack has been returned read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset 38h arbitration lost in sla+r no i2cdat action or 0 0 0 x i 2 c-bus will be released; not addressed slave will be entered no i2cdat action 1 0 0 x a start condition will be transmitted when the bus becomes free
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 13 table 4. slave receiver mode application software response status code status of the i 2 c bus and to i2ccon next action taken by sio hardware (i2csta) sio hardware to/from i2cdat sta sto si aa 60h own sla+w has been received; ack no i2cdat action or x x 0 0 data byte will be received and not ack will be returned has been returned no i2cdat action x x 0 1 data byte will be received and ack will be returned 68h arbitration lost in sla+r/w as master; own sla+w has no i2cdat action or x x 0 0 data byte will be received and not ack will be returned own sla+w has been received, ack returned no i2cdat action x x 0 1 data byte will be received and ack will be returned 80h previously addressed with own slv address; data has read data byte or x x 0 0 data byte will be received and not ack will be returned address; data has been received; ack has been returned read data byte x x 0 1 data byte will be received and ack will be returned 88h previously addressed with own sla; data read data byte or 0 x 0 0 switched to not addressed slv mode; no recognition of own sla byte has been received; not ack read data byte or 0 x 0 1 switched to not addressed slv mode; own sla will be recognized has been returned read data byte or 1 x 0 0 switched to not addressed slv mode; no recognition of own sla. a start condition will be transmitted when the bus becomes free read data byte 1 x 0 1 switched to not addressed slv mode; own sla will be recognized. a start condition will be transmitted when the bus becomes free. a0h a stop condition or repeated start no i2cdat action or 0 x 0 0 switched to not addressed slv mode; no recognition of own sla condition has been received while still no i2cdat action or 0 x 0 1 switched to not addressed slv mode; own sla will be recognized addressed as slv/rec no i2cdat action or 1 x 0 0 switched to not addressed slv mode; no recognition of own sla. a start condition will be transmitted when the bus becomes free no i2cdat action 1 x 0 1 switched to not addressed slv mode; own sla will be recognized. a start condition will be transmitted when the bus becomes free.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 14 table 5. slave transmitter mode application software response status code status of the i 2 c bus and to i2ccon next action taken by sio hardware (i2csta) sio hardware to/from i2cdat sta sto si aa a8h own sla+r has been received; ack load data byte or x x 0 0 last data byte will be transmitted and ack bit will be received has been returned load data byte x x 0 1 data byte will be transmitted; ack will be received b0h arbitration lost in sla+r/w as master; load data byte or x x 0 0 last data byte will be transmitted and ack bit will be received own sla+r has been received, ack has been returned load data byte x x 0 1 data byte will be transmitted; ack bit will be received b8h data byte in i2cdat has been transmitted; load data byte or x x 0 0 last data byte will be transmitted and ack bit will be received ack has been received load data byte x x 0 1 data byte will be transmitted; ack bit will be received c0h data byte in i2cdat has been transmitted; no i2cdat action or 0 x 0 0 switched to not addressed slv mode; no recognition of own sla not ack has been received no i2cdat action or 0 x 0 1 switched to not addressed slv mode; own sla will be recognized no i2cdat action or 1 x 0 0 switched to not addressed slv mode; no recognition of own sla. a start condition will be transmitted when the bus becomes free no i2cdat action 1 x 0 1 switched to not addressed slv mode; own sla will be recognized. a start condition will be transmitted when the bus becomes free. c8h last data byte in i2cdat has been no i2cdat action or 0 x 0 0 switched to not addressed slv mode; no recognition of own sla transmitted (aa = 0); ack has been no i2cdat action or 0 x 0 1 switched to not addressed slv mode; own sla will be recognized received no i2cdat action or 1 x 0 0 switched to not addressed slv mode; no recognition of own sla. a start condition will be transmitted when the bus becomes free no i2cdat action 1 x 0 1 switched to not addressed slv mode; own sla will be recognized. a start condition will be transmitted when the bus becomes free. table 6. miscellaneous states application software response status code status of the i 2 c bus and to i2ccon next action taken by sio hardware (i2csta) sio hardware to/from i2cdat sta sto si aa f8h on reset or stop no i2cdat action 1 x 0 x go into master mode; send start no i2cdat action 0 x 0 0 no recognition of own sla no i2cdat action 0 x 0 1 will recognize own sla 70h bus error sda stuck low reset sio (requires reset to return to state f8h) 90h bus error scl stuck low reset sio (requires reset to return to state f8h) 00h bus error during master or slave mode, due to illegal start or stop condition reset sio (requires reset to return to state f8h)
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 15 slave transmitter mode: in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 5). data transfer is initialized as in the slave receiver mode. when i2cadr and i2ccon have been initialized, sio waits until it is addressed by its own slave address followed by the data direction bit which must be ? 1 ? (r) for sio to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from i2csta. this status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status codes is detailed in table 5. the slave transmitter mode may also be entered if arbitration is lost while sio is in the master mode (see state b0h). if the aa bit is reset during a transfer, sio will transmit the last byte of the transfer and enter state c8h. sio is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer. thus the master receiver receives all 1s as serial data. while aa is reset, sio does not respond to its own slave address. however, the i 2 c-bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate sio from the i 2 c-bus. miscellaneous states: there are four i2csta codes that do not correspond to a defined sio hardware state (see table 6). these are discussed below. i2csta = f8h: this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs on a stop condition and when sio is not involved in a serial transfer. i2csta = 00h: this status code indicates that a bus error has occurred during an sio serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal sio signals. when a bus error occurs, si is set. to recover from a bus error, the microcontroller must send an external reset signal to reset the sio. i2csta = 70h: this status code indicates that the sda line is stuck low when the sio, in master mode, is trying to send a start condition. i2csta = 90h: this status code indicates that the scl line is stuck low. some special cases: the sio hardware has facilities to handle the following special cases that may occur during a serial transfer: ? s imultaneous r epeated start c onditions from t wo m asters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 6). until this occurs, arbitration is not lost by either master since they were both transmitting the same data. if the sio hardware detects a repeated start condition on the i 2 c-bus before generating a repeated start condition itself, it will use the repeated start as its own and continue with the sending of the slave address. ? d ata t ransfer a fter l oss of a rbitration arbitration may be lost in the master transmitter and master receiver modes. loss of arbitration is indicated by the following states in i2csta; 38h, 68h, and b0h (see figures 2 and 3). note: in order to exit state 38h, a timeout, reset, or external stop are required. if the sta flag in i2ccon is set by the routines which service these states, then, if the bus is free again, a start condition (state 08h) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. ? f orced a ccess to the i 2 c b us in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c-bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c-bus is possible. if the i 2 c-bus stays idle for a time period equal to the time out period, then the ? 64 concludes that no other master is using the bus and sends a start condition. s 08h sla w a data a s both masters continue with sla transmission 18h 28h other master sends repeated start condition earlier su00975 figure 6. simultaneous repeated start conditions from 2 masters
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 16 sta flag time out sda line scl line start condition su00976 figure 7. forced access to a busy i 2 c-bus ? i 2 c b us o bstructed by a low l evel on scl or sda an i 2 c-bus hang-up occurs if sda or scl is pulled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the sio hardware cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. when the scl line stays low for a period equal to the time-out value, the ? 64 concludes that this is a bus error and behaves in a manner described on page 5 under ? time-out register ? . if the sda line is obstructed by another device on the bus (e.g., a slave device out of bit synchronization), the problem can be solved by transmitting additional clock pulses on the scl line (see figure 8). the sio hardware sends out nine clock pulses followed by the stop condition. if the sda line is released by the slave pulling it low, a normal start condition is transmitted by the sio, state 08h is entered and the serial transfer continues. if the sda line is not released by the slave pulling it low, then the sio concludes that there is a bus error, loads 70h in i2csta, generates an interrupt signal, and releases the scl and sda lines. after the microcontroller reads the status register, it needs to send an external reset signal in order to reset the sio. if a forced bus access occurs or a repeated start condition is transmitted while sda is obstructed (pulled low), the sio hardware performs the same action as described above. in each case, state 08h is entered after a successful start condition is transmitted and normal serial transfer continues. note that the cpu is not involved in solving these bus hang-up problems. ? b us e rror a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. the sio hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, sio releases the sda and scl lines, sets the interrupt flag, and loads the status register with 00h. this status code may be used to vector to a service routine which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 6. the microcontroller must send an external reset signal to reset the sio. sta flag sda line scl line su01663 123456789 start condition stop condition figure 8. recovering from a bus obstruction caused by a low level on sda
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 17 i 2 c-bus timing diagrams the diagrams (figures 9 to 12) illustrate typical timing diagrams for the pca9564 in master/slave functions. master pca9564 writes data to slave transmitter. su01490 7-bit address stop condition first-byte r/w = 0 interrupt interrupt interrupt nbyte ack ack ack from slave receiver scl sda int start condition figure 9. bus timing diagram; master transmitter mode su01491 master pca9564 reads data from slave transmitter. 7-bit address stop condition first-byte r/w = 1 interrupt interrupt nbyte ack ack no ack from slave from master receiver scl sda int start condition figure 10. bus timing diagram; master receiver mode
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 18 su14092 external master receiver reads data from pca9564. 7-bit address start condition stop condition first-byte r/w = 1 interrupt interrupt interrupt nbyte scl sda int ack ack no ack from slave pca9564 from master receiver figure 11. bus timing diagram; slave transmitter mode su01493 slave pca9564 is written to by external master transmitter. 7-bit address start condition stop condition first-byte r/w = 0 interrupt interrupt interrupt nbyte scl sda int ack ack ack from slave pca9564 interrupt (after stop) figure 12. bus timing diagram; slave receiver mode
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 19 sd00705 pca9564 80c51 address bus decoder d[0:7] ale ce rd wr int a0 scl sda a1 v dd 8 v dd reset v dd v ss slave v dd int reset v ss v dd figure 13. application diagram using the 80c51
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 20 specific applications the pca9564 is a parallel bus to i 2 c bus controller that is designed to allow ? smart ? devices to interface with i 2 c or smbus components , where the ? smart ? device does not have an integrated i 2 c port and the designer does not want to ? bit-bang ? the i 2 c port. the pca9564 can also be used to add more i 2 c ports to ? smart ? devices, provide a higher frequency, lower voltage migration path for the pcf8584 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the pc board. add i 2 c bus port as shown in figure 14, the pca9564 converts 8-bits of parallel data into a multiple master capable i 2 c port for microcontrollers, microprocessors, custom asics, dsps, etc., that need to interface with i 2 c or smbus components. microcontroller, microprocessor, or asic control signals 8-bits pca9564 scl sda sw02108 figure 14. adding i 2 c bus port application add additional i 2 c bus ports the pca9564 can be used to convert 8-bit parallel data into additional multiple master capable i 2 c port as shown in figure 15. it is used if the microcontroller, microprocessor, custom asic, dsp, etc., already have an i 2 c port but need one or more additional i 2 c ports to interface with more i 2 c or smbus components or components that cannot be located on the same bus (e.g., 100 khz and 400 khz slaves on different buses so that each bus can operate at its maximum potential). microcontroller, microprocessor, or asic control signals 8-bits pca9564 scl sda scl sda sw02109 figure 15. adding additional i 2 c bus ports application pca8584 migration path the pca9564 does the same type of parallel to serial conversion as the pcf8584. although not footprint or code compatible, the pca9564 provides improvements such as: 1. operating at 3.3 v and 2.5 v voltage nodes with 5 v tolerant i/os 2. allows interface with i 2 c or smbus components at speeds up to 400 khz. 3. built-in oscillator provides a cost effective solution since the external clock input is no longer required. 4. parallel data can be exchanged at speeds up to 50 mhz allowing the use of faster processors. pca9564 scl sda oscillator pcf8584 scl sda clock input 2.3 - 3.6 v < 400 khz 4.5 - 5.5 v < 1 00 khz sw02110 supply voltage frequency figure 16. pcf8584 migration path convert 8 bits of parallel data into i 2 c serial data stream functioning as a slave transmitter, the pca9564 can convert 8-bit parallel data into a two-wire i 2 c data stream as is shown in figure 17. this would prevent having to run 8 traces across the entire width of the pc board. microcontroller, microprocessor, or asic control signals 8-bits pca9564 scl sda master sw02111 figure 17. converting parallel to serial data application
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 21 absolute maximum ratings in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min max unit v dd supply voltage -0.3 4.6 v v i voltage range (any input) -0.8 6.0 1 v i i dc input current (any input) -10 10 ma i o dc output current (any output) -10 10 ma p tot total power dissipation ? 300 mw p o power dissipation per output ? 50 mw t amb operating ambient temperature -40 +85 c t stg storage temperature -65 +150 c note: 1. 5.5 v steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 v steady sta te voltage tolerance on inputs and outputs when no supply voltage is present. handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirab le to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under ? handling mos devices ? . dc characteristics v dd = 2.3 v to 3.6 v; t amb = -40 to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 ? 3.6 v standby ? 0.1 3.0 a i dd supply current operating - no load ? ? 6.0 ma v por power-on reset voltage ? 1.8 2.2 v inputs wr , rd , a0, a1, ce , reset v il low level input voltage 0 ? 0.8 v v ih high level input voltage 2.0 ? 5.5 1 v i l leakage current input; v i = 0 v or 5.5 v -1 ? 1 a c i input capacitance v i = v ss or v dd ? 1.7 3 pf inputs/outputs d0 to d7 v il low level input voltage 0 ? 0.8 v v ih high level input voltage 2.0 ? 5.5 1 v i oh high level output current v oh = v dd - 0.4 v -4.0 -7.0 ? ma i ol low level output current v ol = 0.4 v 4.0 8.0 ? ma i l leakage current input; v i = 0 v or 5.5 v -1 ? 1 a c io input/output capacitance v i = v ss or v dd ? 2.4 4 pf sda and scl v il low level input voltage 0 ? 0.3 v dd v v ih high level input voltage 0.7 v dd ? 5.5 1 v input/output; v i = 0 v or 3.6 v -1 ? 1 ? 10 a i ol low level output current v ol = 0.4 v 5.0 8.5 ? ma c io input/output capacitance v i = v ss or v dd ? 2.5 4 pf outputs int i ol low level output current v ol = 0.4 v 3.0 ? ? ma i l leakage current v o = 0 or 3.6 v -1 ? 1 a c o output capacitance v i = v ss or v dd ? 2.1 4 pf note: 1. 5.5 v steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 v steady sta te voltage tolerance on inputs and outputs when no supply voltage is present.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 22 sda scl su01755 t hd;sta t f s t low t r t hd;dat t su;dat t high t f t su;sta s r t hd;sta t sp t su;sto p t r t buf s figure 18. definition of timing i 2 c-bus timing specifications all the timing limits are valid within the operating supply voltage and ambient temperature range; v dd = 2.5 v 0.2 v and 3.3 v 0.3 v, t amb = -40 to +85 c; and refer to v il and v ih with an input voltage of v ss to v dd . symbol parameter standard mode i 2 c bus fast mode i 2 c bus units symbol parameter min max min max units f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 ? 1.3 ? s t hd;sta hold time after (repeated) start condition 4.0 ? 0.6 ? s t su;sta repeated start condition setup time 4.7 ? 0.6 ? s t su;sto setup time for stop condition 4.0 ? 0.6 ? s t hd;dat data in hold time 0 ? 0 ? ns t vd;ack valid time for ack condition ? 0.6 ? 0.6 s t vd;dat(l) data out valid time low ? 0.6 ? 0.6 s t vd;dat(h) data out valid time high ? 0.6 ? 0.6 s t su;dat data setup time 250 ? 100 ? ns t low clock low period 4.7 ? 1.3 ? s t high clock high period 4.0 ? 0.6 ? s t f clock/data fall time ? 0.3 ? 0.3 s t r clock/data rise time ? 1 ? 0.3 s t sp pulse width of spikes that must be suppressed by the input filters ? 50 ? 50 ns
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 23 sda scl sw02107 t res t res 50% 30% 50% 50% 50% t rec t wres reset dn led off ack or read cycle start figure 19. reset timing a0-a1 ce t as t cs t ch rd t rw t rwd d0-d7 (read) t dd t df float float valid wr t rwd valid d0-d7 (write) t ds t dh t ah sd00711 figure 20. bus timing
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 24 ac characteristics (3.3 volt) 1, 2, 3 v cc = 3.3 v 3.0 v, t amb = -40 to +85 c, unless otherwise specified. (see page 25 for 2.5 v.) limits symbol parameter min max unit reset timing (see figure 19) t wres reset pulse width 10 ? ns t res 4,5 time to reset 250 ? ns t rec reset recovery time 0 ? ns bus timing (see figure 20, 21) t as a0-a1 setup time to rd , wr low 0 ? ns t ah a0-a1 hold time from rd , wr low 7 ? ns t cs ce setup time to rd , wr low 0 ? ns t ch ce hold time from rd , wr low 0 ? ns t rw wr , rd pulse width (low time) 7 ? ns t dd data valid after rd and ce low ? 17 ns t df data bus floating after rd or ce high ? 17 ns t ds data bus setup time before wr or ce high (write cycle) 7 ? ns t dh data hold time after wr high 0 ? ns t rwd high time between read and/or write cycles 12 ? ns notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0 v and 3.0 v with a transitio n time of 5 ns maximum. all time measurements are referenced at input voltages of 1.5 v and output voltages shown in figures 20-21. 3. test conditions for outputs: c l = 50 pf, r l = 500 ? , except open drain outputs. test conditions for open drain outputs: c l = 50 pf, r l = 1 k ? pullup to v dd . 4. resetting the device while actively communicating on the bus may cause glitches or an errant stop condition. 5. upon reset, the full delay will be the sum of t res and the rc time constant of the sda and scl bus.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 25 ac characteristics (2.5 volt) 1, 2, 3 v cc = 2.5 v 0.2 v, t amb = -40 to +85 c, unless otherwise specified. (see page 24 for 3.3 v.) limits symbol parameter min max unit reset timing (see figure 19) t wres reset pulse width 10 ? ns t res 4,5 time to reset 250 ? ns t rec reset recovery time 0 ? ns bus timing (see figure 20, 21) t as a0-a1 setup time to rd , wr low 0 ? ns t ah a0-a hold time from rd , wr low 9 ? ns t cs ce setup time to rd , wr low 0 ? ns t ch ce hold time from rd , wr low 0 ? ns t rw wr , rd pulse width (low time) 9 ? ns t dd data valid after rd and ce low ? 22 ns t df data bus floating after rd or ce high ? 17 ns t ds data bus setup time before wr or ce high (write cycle) 8 ? ns t dh data hold time after wr high 0 ? ns t rwd high time between read and/or write cycles 12 ? ns notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0 v and 3.0 v with a transitio n time of 5 ns maximum. all time measurements are referenced at input voltages of 1.5 v and output voltages shown in figures 20-21. 3. test conditions for outputs: c l = 50 pf, r l = 500 ? , except open drain outputs. test conditions for open drain outputs: c l = 50 pf, r l = 1 k ? pullup to v dd . 4. resetting the device while actively communicating on the bus may cause glitches or an errant stop condition. 5. upon reset, the full delay will be the sum of t res and the rc time constant of the sda and scl bus.
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 26 rd , ce input v m v m dn output low-to-float float-to-low v i gnd v cc t dd(zl) v oh v ol t df(lz) sw02113 gnd v m v m v y v x dn output high-to-float float-to-high outputs enabled outputs enabled outputs floating t df(hz) t dd(zh) v m = 1.5 v v x = v ol + 0.3 v v y = v oh - 0.3 v v ol and v oh are typical output voltage drops that occur with the output load. figure 21. t dd and t df times test s1 t dd(zh)/ t df(hz) 6 v t dd(zl)/ t df(lz) open pulse generator v i v o c l 50pf v cc definitions r l = load resistor. c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generators. 6.0 v r t r l = 500 ? open d.u.t. r l = 500 ? sw02114 figure 22. test circuitry for switching times
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 27 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 28 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 29 hvqfn20: plastic, heatsink very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm sot662-1
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 30 revision history rev date description _2 20030402 product data (9397 750 11353): ecn 853-2419 29715 dated 24 march 2003. supersedes objective data of 2003 feb 26 (9397 750 11153). ? upgrade data sheet status from objective to product data. _1 20030226 objective data (9397 750 11153)
philips semiconductors product data pca9564 parallel bus to i 2 c-bus controller 2003 apr 02 31 purchase of philips i 2 c components conveys a license under the philips ? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 04-03 document order number: 9397 750 11353 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

▲Up To Search▲

Price & Availability of PCA9564D

	To Download PCA9564D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .